__   _ __      _  __

       / /  (_) /____ | |/_/

      / /__/ / __/ -_)>  <

     /____/_/\__/\__/_/|_|

   Build your hardware, easily!


 (c) Copyright 2012-2024 Enjoy-Digital

 (c) Copyright 2007-2015 M-Labs


 BIOS built on Nov 10 2026 08:47:26

 BIOS CRC passed (c5212fc5)


 LiteX git sha1: --------


--=============== SoC ==================--

CPU:		VexRiscv @ 48MHz

BUS:		wishbone 32-bit @ 4GiB

CSR:		32-bit data

ROM:		32.0KiB

SRAM:		8.0KiB

L2:		128B

SDRAM:		8.0MiB 32-bit @ 48MT/s (CL-2 CWL-2)

MAIN-RAM:	8.0MiB


--========== Initialization ============--


Initializing SDRAM @0x40000000...

Switching SDRAM to software control.

Switching SDRAM to hardware control.

Memtest at 0x40000000 (2.0MiB)...



Memtest OK

Memspeed at 0x40000000 (Sequential, 2.0MiB)...

  Write speed: 20.4MiB/s

   Read speed: 24.2MiB/s


--============== Boot ==================--

Booting from serial...

Press Q or ESC to abort boot completely.

sL5DdSMmkekro
Executing booted program at 0x40000000


--============= Liftoff! ===============--

*** Booting Zephyr OS build 684c9e8f32e4 ***

ExecuTorch on tang_nano_20k/litex_vexriscv (Zephyr 4.4.0)
model: 62888 bytes, method pool 131072 B, temp pool 16384 B
I [executorch:main.cpp:118 init()] planned buffer 0: 52928 bytes
I [executorch:main.cpp:148 init()] method 'forward' loaded; pool used 59584 / 131072 bytes
  logit[0] =   -1.2525
  logit[1] =   -2.3244
  logit[2] =    4.0803
  logit[3] =    2.5802
  logit[4] =   -5.6759
  logit[5] =   -5.8199
  logit[6] =   -7.9416
  logit[7] =   10.5990  <-- argmax
  logit[8] =   -2.2308
  logit[9] =   -0.1515
self-test: predicted 7, expected 7, max |device - pytorch| = 3.34e-06, 2956822 us
SELF-TEST PASS
inference: 2956766 us average over 10 runs at 48 MHz